HDD Servo Processing Subsystem Architecture Lead at Western Digital | Job-Scouts.com

HDD Servo Processing Subsystem Architecture Lead

Western Digital
full-time lead San Jose, CA, United States · More jobs in San Jose, California, United States
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Job Description

Senior Manager, Servo Firmware Engineering Location: San Jose, CA or Irvine, CA,

About the Role

We are seeking an experienced Senior Manager to join our organization in San Jose, CA or Irvine, CA, United States. In this role, you will lead the US HDD servo firmware development team responsible for the strategic vision and execution of the servo subsystem firmware architecture to enable next-generation HDD products with multiple concurrent data streams and multi-actuator control. You will be accountable for defining a coherent, scalable platform strategy that balances technical feasibility with economic viability across program schedules, power envelopes, and cost constraints.

Essential Duties and Responsibilities

· Collaborate with cross-functional stakeholders — including SoC architecture, recording systems, and manufacturing teams — to define and implement HDD servo firmware encompassing real-time motion control, parameter management, microarchitecture, instruction set architecture, and associated toolchains.

• Facilitate and participate in team meetings and lead firmware and associated tooling development, maintaining clear and sufficient communication for a geographically distributed international development team to support business and technical objectives.
• Define hardware, firmware, and associated tools designs together with stakeholders and development teams.
• Negotiate with stakeholders on priority and ensure strong execution of identified hardware, firmware, and associated tools strategy.
• Enable definition and maintenance of a future-state servo real-time control firmware architecture that scales from single to multiple concurrent data streams and supports concurrent control of multiple actuators and heads.
• Coordinate SoC microarchitecture decisions affecting servo compute, including core count, memory hierarchy, interconnect design, and dynamic control accelerators, ensuring that FPGA prototype work and accelerator designs map cleanly into production-ready firmware and tools models.
• Own servo compute resource management and budgeting, including instruction and data memory allocation, processor cycle limits, and regression thresholds; drive adherence through continuous integration practices to prevent late-stage resource conflicts.
• Lead the co-design of firmware platform architecture, including core control-loop implementations, multi-cluster and multi-actuator orchestration, and cross-generation stability, ensuring deterministic real-time performance across multiple SoC generations.
• Drive the evolution of the servo firmware tools ecosystem to support multi-cluster, multi-stream characterization and debugging.
• Coordinate across geographically distributed teams — including servo firmware, SoC architecture and design, recording subsystem and algorithms, servo tools, manufacturing firmware, and test — to align platform decisions with program risk, schedules, yield, and customer experience objectives.
• Deliver major multi-stream and multi-actuator capabilities that meet control performance and power targets on new SoC generations.
• Communicate technical concepts, architectural trade-offs, and strategic recommendations to senior management and cross-functional stakeholders, providing architectural guidance throughout the product development lifecycle.

Requirements

Function: Engineering
Experience Level: Director

Location

San Jose, CA, United States
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