VP of HW Systems Engineering at Axiado | Job-Scouts.com

VP of HW Systems Engineering

Axiado
full-time director San Jose, CA, United States · More jobs in San Jose, California, United States
This position is sourced from Axiado's career page . Apply through Job-Scouts to track your application status.

Prefer a full account with a password? Sign Up to Apply

Job Description

Job Summary

We are seeking an agile, results-driven VP of HW Systems Engineering to lead our hardware organization. In this highly visible role, you will own the hardware product lifecycle from concept to high-volume production for the Axiado Trusted Control/Compute Unit (TCU) products. This role requires an executive with elite, hands-on design and debugging capabilities who thrives in the lab and effectively navigates dynamic, supply-chain-constrained environments. You will manage senior engineers and contractors, help customers build secure server infrastructure, and champion open hardware ecosystems like the Open Compute Project (OCP).

Key Responsibilities

• Leadership & Execution: Drive TCU-based embedded systems from initial concept through high-volume production with active, hands-on daily execution.
• Mass Production & Yield: Take complex boards to mass production while optimizing DFM/DFT, factory test coverage, and production yields.
• Sustaining & RMA Support: Oversee the technical resolution of customer field returns, driving Failure Analysis (FA) and corrective actions to improve reliability.
• Root-Cause Triage: Partner with cross-company ASIC, silicon, firmware, and software teams to systematically isolate and resolve complex system bugs.
• Lab Validation: Personally lead first-silicon and platform bring-up, low-level bus validation, and EVT/DVT testing in the lab.
• OCP & Industry Forums: Integrate OCP DC-SCM standards and represent the company within OCP and other industry hardware forums.
• Supply Chain Agility: Pivot board layouts responsively based on real-time parts availability and manage critical tier-1 supplier relationships.
• Design & Review: Drive schematic development in Cadence OrCAD and collaborate with Layout, Mechanical, and SI engineers to meet OCP DC-SCM and NVIDIA IFF form factors.

Requirements

Department: Hardware
Function: Engineering
Experience Level: Mid-Senior Level

Required Skills

Location

San Jose, CA, United States
View on Google Maps

Similar open positions