Semiconductor Layout & Tape-Out Engineer
Job Description
Position Overview
The Layout Tape-Out Support Engineer is responsible for end-to-end tape-out execution for Gallium Nitride (GaN) technologies. This role supports multiple concurrent tape-out flows, ensuring accurate, high-quality mask data delivery while enabling effective collaboration across global and Japanese-speaking teams.
Key Responsibilities
Layout & Design Support
Perform and support PCM (Process Control Monitor) layout development and verification. Design and maintain alignment mark layouts in compliance with lithography and process requirements. Support stepper reticle 1:1 aligner mask layout generation, validation, and optimization.
Run Design Rule Checks (DRC) and mask data validation.
Tape-Out Flow Management
Support tape-out operations across multiple flows, ensuring schedule adherence and high-quality deliverables. Collaborate with global and Japanese-speaking stakeholders to drive alignment across design, process, and mask vendors. Provide operational support for tape-out activities; Fluent communication skills in both Japanese and English are required.
Mask Data Preparation & Signoff
Execute mask data generation workflows in accordance with foundry requirements. Perform mask data verification and signoff, ensuring format accuracy and rule compliance. Conduct MEBES data checks to ensure mask write readiness.
Mask Ordering & Logistics
Manage tape-out (TO) submissions and mask ordering processes. Track purchase orders (POs) associated with mask fabrication. Coordinate with mask vendors on scheduling, delivery, and issue resolution.
Quality & Compliance
Perform thorough verification of mask data integrity, PCM structures, and alignment features. Ensure all deliverables comply with internal standards and external vendor specifications.
Requirements
Function: Engineering
Experience Level: Mid-Senior Level