Senior Staff/Principal Engineer, Digital Design (Power & Analog ICs)

We are seeking a Senior Staff Digital Design Engineer to architect and implement the digital content within power, analog, and mixed-signal IC products. This is a senior individual-contributor role requiring ownership from requirements and microarchitecture through RTL, synthesis, timing closure, DFT support, and silicon bring-up. 

The successful candidate will design control, sequencing, protection, diagnostics, trimming, communication, test, and safety-related logic that works closely with analog circuitry. The emphasis is not on large processor SoCs. It is on high-quality digital design embedded inside power and analog ICs. 

You will be expected to resolve ambiguous requirements, make sound area-power-performance trade-offs, develop reusable design practices, mentor engineers, and collaborate across analog design, verification, physical design, test, applications, and product teams. 

Responsibilities :

Digital Architecture & RTL Design 

• Translate product and circuit requirements into robust digital microarchitecture and detailed block specifications. 

• Design optimized RTL for control, sequencing, protection, diagnostics, trimming, communication, test, and low-power functions within power and analog ICs. 

• Own block-level integration and contribute to chip-level digital architecture, interfaces, clocking, reset, power-state, and register-map decisions. 

• Make and document trade-offs across functionality, area, power, testability, timing, reuse, and implementation risk. 

Implementation, Timing & DFT 

• Develop synthesizable Verilog/SystemVerilog RTL, synthesis scripts, timing constraints, and implementation collateral. 

• Own or guide synthesis, lint, CDC/RDC, low-power checks, static timing analysis, and handoff to physical design. 

• Support DFT architecture and implementation, including scan insertion, ATPG enablement, test modes, and production-test requirements. 

• Work with place-and-route teams on timing closure, congestion, power, and post-layout issues. 

Verification & Silicon Support 

• Collaborate with verification engineers on verification planning, assertions, coverage, debug, and specification closure. 

• Develop directed tests, reference checks, or test vectors where useful to accelerate design validation and production-test development. 

• Support gate-level and post-layout verification, silicon bring-up, device evaluation, failure analysis, and root-cause investigation. 

• Develop and document practical workarounds where device errata or silicon limitations require them. 

Technical Leadership & Reuse 

• Drive reusable RTL, design methodology, coding standards, review practices, and automation across projects. 

• Mentor junior and mid-level digital engineers and lead architecture, RTL, and implementation reviews. 

• Identify technical and schedule risks early and communicate clear options and recommendations to project leadership. 

• Collaborate effectively with analog, applications, test, layout, CAD, and product teams across global locations.

Function: Manufacturing
Experience Level: Mid-Senior Level