Staff Package Design Engineer - Cu FSM/BGBM/Bumping 封装设计专家

• Design and develop package and interconnect methods for Renesas’s packaging needs in the areas of Power SiP/modules, wafer level chip scale package,  flip-chip, multi-chip module LGA and power device packaging.
• Strong understanding on wafer processing such as Cu Front side of metal/Backgrind Backmetal, Taiko Backgrinding, Glass carrier bonding&grinding;, Patterned back metal, Cu pillar bumping technology.
• Package technologies qualification for consumer & industrial power as well as automotive power applications.
• Benchmark, select and qualify suitable materials, processes and assembly subcontractors (OSAT) or contract manufacturers (CM).
• Work with OSAT/CM  to develop, run DOE to optimize processes and establish process spec.
• Work with Product groups and Reliability team, qualify new packages and processes within required time frame.
• Resolve all process integration issues by ensuring all window checks are done on critical process steps.
• Establish production controls and monitor to ensure there is no room for quality incidents.
• Ensure smooth transition into production & implement ramp up monitor.  
• Work with OSAT/CM  to monitor and resolve process issues early in the production to ensure only parts with superior quality shipped to customer.
• Develop and maintain technical expertise on advances and innovations in power SiP/modules, wafer level packaging & flip chip interconnects.
• Participate in packaging roadmap development & focus on execution.
• Address internal and external customer complains working with peers of Marketing, Product groups, Quality and Operations organization to satisfy growth in businesses.
• Establish & maintain package design rules.

Function: Engineering
Experience Level: Mid-Senior Level