Principal Engineer, RTL Design

SoC Architecture & Integration

• Lead integration of complex multi-billion transistor SoCs comprising CPUs, GPUs, NPUs, AI accelerators, memory subsystems, and high-speed peripherals.
• Define and implement scalable SoC architectures, subsystem partitioning, and integration strategies.
• Drive top-level RTL integration, IP assembly, and system-level design closure.
• Collaborate with architecture, verification, physical design, DFT, firmware, and software teams throughout the development lifecycle.
NoC & Interconnect Architecture

• Architect and integrate advanced Network-on-Chip (NoC) solutions for high-bandwidth and low-latency data movement.
• Optimize traffic flows, QoS, coherency, memory access, and interconnect performance.
• Define clocking, reset, and power strategies across complex interconnect fabrics.
High-Speed Interfaces & Protocols

• Lead integration and implementation of industry-standard interfaces including:• UCIe
• PCIe
• DDR/LPDDR
• CXL
• Ethernet
• High-speed SerDes

• Drive protocol compliance, performance optimization, and subsystem-level integration.
Compute & AI Subsystems

• Integrate and optimize heterogeneous compute architectures involving:• Multi-core CPUs
• NPUs
• GPUs
• AI/ML Accelerators

• Drive system-level performance, coherency, memory hierarchy, and scalability considerations.
Functional Safety & Security

• Define and implement hardware architectures supporting Functional Safety requirements (ISO 26262 and related standards).
• Develop safety mechanisms including redundancy, fault detection, fault isolation, and diagnostic coverage.
• Drive hardware security architecture including secure boot, key management, access control, and protection mechanisms.
Low-Power Design & UPF

• Lead SoC low-power architecture and implementation.
• Define and review UPF-based power intent for complex multi-voltage, multi-power-domain designs.
• Drive power-aware RTL integration and verification.
• Implement advanced low-power techniques including:• Power gating
• Clock gating
• Voltage islands
• Retention strategies
• Dynamic power management

Clock & Reset Architecture

• Define and implement complex SoC clocking and reset architectures.
• Drive clock-domain crossing (CDC) and reset-domain crossing (RDC) methodologies.
• Collaborate with implementation teams for timing closure and clock distribution optimization.
Technical Leadership

• Provide technical leadership and mentoring to RTL and integration engineers.
• Drive design reviews, architecture reviews, and methodology improvements.
• Establish best practices for RTL quality, integration, low-power implementation, and design signoff.
• Influence product roadmap and technology strategy through technical expertise.

Function: Manufacturing
Experience Level: Mid-Senior Level