Sr Staff /Staff Engineer, RTL Design

• Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications.
• Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning.
• Lead RTL design and integration of multi-subsystem SoCs, supporting complex architectures with multi-core, multi-power, and multi-reset domains.
• Demonstrate strong proficiency with front-end flows, including Lint, CDC, low-power (UPF) checks, synthesis, DFT, and Static Timing Analysis (STA).
• Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects.
• Design and integrate standard interface protocols such as AHB, AXI, CHI, and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4.
• Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery.
• Support post-silicon debug, bring-up, and validation, working closely with lab and silicon validation teams.
• Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle.
• Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals.
• Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc.

Function: Manufacturing
Experience Level: Mid-Senior Level