Sr EDA Engineer

Job Description

· Work as part of an established EDA team to maintain, support, and enhance a production RTL-to-Gates implementation, static verification, and signoff flow

· Provide hands-on support to global project teams (Europe, India, US) to ensure effective adoption and execution of the flow

· Develop, debug, and maintain flow infrastructure using industry-standard EDA tools (primarily Synopsys)

· Investigate and resolve user issues, ensuring robust, scalable, and production-quality flow operation across multiple concurrent projects

· Contribute to continuous improvement of flow capabilities, including:

o Automation enhancements

o Standardisation of reporting

o QoR, Power, and runtime optimisation

· Work closely with a highly experienced global team to deploy best practices and ensure consistency across projects

· Support flow migration activities to next-generation corporate implementation platform, including:

o Porting scripts and custom reporting

o Validation and testing of migrated flows

o Supporting user onboarding and transition

· Collaborate actively with EDA solution development, deployment, and support teams in Vietnam, contributing to a strong and growing Digital Backend capability

· Follow disciplined software engineering practices in flow development (version control, modularisation, documentation)

· Participate in cross-site coordination and continuous improvement initiatives to improve overall delivery quality and efficiency

Technical Experience:

• Practical experience with RTL-to-Gates implementation and signoff flows, including:

o Synthesis

o Static timing analysis

o Power Analysis

o Lint / CDC / RDC or related static checks

• Hands-on experience with Synopsys tools (preferred), or equivalent industry tools

• Strong scripting and automation skills (e.g., Tcl, Python, or Perl)

• Understanding of EDA flow integration, batch execution, and debugging methodologies

Methodology & Advanced Capability:

· Experience with constraint development and debugging, including:

o SDC creation and validation

o Timing constraint development

o Clock definition and clocking strategies

· Understanding of low-power design methodologies, including:

o UPF / CPF concepts

o Impact of power intent on implementation and signoff flows

· Familiarity with hierarchical and large-scale SoC design methodologies

· Experience analysing and optimising QoR trade-offs, including:

o Timing vs area vs power

o Trade-offs across implementation stages

General Skills:

• Strong problem-solving skills and ability to diagnose complex technical issues

• Comfortable working in a global, multi-site environment with cross-functional teams

• Good communication skills (written and verbal) and ability to support end users effectively

• Self-motivated with a “can-do” attitude and strong ownership of deliverables

• Ability to learn quickly and adapt to new tools, technologies, and methodologies

Function: Manufacturing
Experience Level: Mid-Senior Level