NAND Array Engineer

Solidigm is looking for a highly motivated and technically skilled NAND Array Engineer to join our Performance and Reliability Team. In this role, you will play a critical part in shaping the future of 3D NAND technology by driving characterization of array erase, program, and read operations, and leading trim development for next-generation products. You will work at the intersection of device physics, data analysis, and cross-functional collaboration to deliver industry-leading NAND solutions.

Key Responsibilities:

• Design, plan, and execute NAND memory cell and array characterization experiments to evaluate performance and reliability.
• Develop and optimize trims to improve Read Window Budget (RWB) and Raw Bit Error Rate (RBER), directly impacting product quality.
• Apply NAND device physics principles to explain and interpret relationships between experimental data and trim parameters.
• Collaborate cross-functionally with Device, Design, Reliability, and Product/Test Engineering teams to design and execute bench experiments.
• Interface with wafer fabrication teams to drive Sort and Wafer-Level Reliability (WLR) Design of Experiments (DOEs).
• Conduct comprehensive data analysis to identify and communicate trade-offs across multiple parameters of interest.
• Build predictive models for NAND behavior based on empirically observed data.
• Develop and maintain scorecards to track NAND device degradation through various physical mechanisms over time.
• Release optimized trims to the production flow on a regular cadence to ensure continuous product improvement.
• Drive improvements in back-end test yields through trim optimization and advanced screening techniques.

Department: NAND Development
Function: Other
Experience Level: Not Applicable