Associate Hardware Engineer

• Develop and optimize custom layout implementations for IO (GPIO, Peripheral IO), Power, and Hard Macro IPs on advanced semiconductor technologies (e.g. TSMC, GlobalFoundries...), working closely with technical experts from both Japan and Vietnam teams.
• Perform full-custom layout design for IO circuits, analog circuits, and low-power control circuits from schematic implementation through final layout release, ensuring compliance with IP specifications and quality requirements.
• Conduct floorplan, device placement, routing, and layout optimization of hierarchical IP blocks while adhering to technology design rules, quality assurance standards, and manufacturability requirements.
• Ensure designs achieve targets for performance, power, area, reliability, ESD robustness, and silicon manufacturability.
• Execute physical verification activities including DRC, LVS, ERC, Antenna, and related validation checks, and perform root-cause analysis and debugging of verification issues.
• Generate and maintain IP deliverables and library collateral, including GDSII, CDL, LEF, Liberty, NDM, and associated documentation required for downstream implementation flows.
• Collaborate with Chip Top, Product, and Physical Design teams to support integration, verification, and PPA (Performance, Power, Area) optimization at the chip level.
• Analyze and address reliability concerns, including ESD, Electromigration (EM), IR Drop, and Latch-up, throughout the IP development cycle.
• Drive productivity and quality improvements through methodology enhancement, automation development, and continuous process optimization.

Function: Manufacturing
Experience Level: Associate