Staff Digital Verification Engineer

Job Description:

Renesas is seeking a Staff Digital Design Verification Engineer to join our team developing complex power management SoCs. These products integrate digital control, telemetry, fault management, communication interfaces, configurable peripherals, and advanced power-control functions for AI, datacenter, enterprise computing, networking, and high-performance power delivery applications.

You will independently own verification of significant blocks and features from planning through closure. The role combines hands-on UVM development, coverage-driven verification, complex debug, and close collaboration with architecture, RTL design, firmware, analog, validation, and systems teams.

Responsibilities:

• Own verification of complex digital blocks or major SoC features from requirements analysis through coverage closure.
• Develop feature-based verification plans from product, architecture, and microarchitecture specifications; identify gaps, ambiguities, corner cases, and risks.
• Build and extend reusable SystemVerilog/UVM environments, including sequences, monitors, scoreboards, checkers, assertions, and coverage models.
• Develop constrained random and targeted tests for normal operation, error handling, recovery, and system-level interactions.
• Drive functional, code, toggle, FSM, and assertion coverage closure using regression and coverage data.
• Debug RTL, testbench, assertion, integration, and regression failures; collaborate with design and firmware teams to isolate issues and verify fixes.
• Automate regression, triage, reporting, and analysis workflows using scripting and modern engineering tools.
• Communicate status, risks, dependencies, and closure evidence clearly; provide technical guidance to less-experienced engineers.

Function: Manufacturing
Experience Level: Mid-Senior Level