Senior/Staff Verification Engineer

We are looking for an experienced Senior or Staff Verification Engineer to play a key role in the functional verification of complex digital ICs for automotive and industrial applications. In this role, you will drive verification activities from requirements analysis through coverage-driven sign-off, leveraging strong SystemVerilog/UVM expertise while contributing to reusable methodologies, process improvements, and the growth of less-experienced team members.

Key Responsibilities

• Analyze product requirements, architectures, and design specifications to define verification strategies, risks, dependencies, and acceptance criteria.
• Create and maintain verification plans, ensuring clear requirements traceability, coverage objectives, and sign-off readiness.
• Develop and enhance reusable SystemVerilog/UVM verification environments, including agents, sequences, scoreboards, reference models, and coverage solutions.
• Design and execute constrained-random, directed, error-injection, assertion-based, and formal verification test scenarios.
• Drive regressions, debug verification and design issues, collaborate closely with design engineers, and ensure timely defect closure.
• Measure, analyze, and close functional, code, and assertion coverage gaps to achieve verification quality and sign-off goals.
• Contribute to system-level verification, technical reviews, automation initiatives, continuous improvement efforts, and mentoring of junior engineers.

Function: Engineering
Experience Level: Mid-Senior Level