Senior Staff Electrical Engineer

Renesas is seeking a Senior Staff Digital Design Verification Engineer to lead verification

architecture, methodology and signoff for our Austin team's digitally controlled power-management

ICs, which power datacenter, AI accelerator, enterprise computing and networking systems. These

chips combine a multiphase digital control loop, telemetry, fault and alert management, PMBus,

AVSBus and high-speed power-management bus interfaces, an embedded microcontroller running

production firmware, and non-volatile configuration, all integrated with high-performance analog.

This is a hands-on technical leadership role. You will own the verification strategy and tapeout

signoff for a controller program, architect the UVM-based environment in which our next generation

of controllers will be verified, lead the migration of a large, mature directed-random SystemVerilog

environment and its regression suite onto that platform, and raise the technical level of the

verification team through review and mentorship. You set direction and are accountable for the

result, while still writing testbench code, debugging the hardest failures and making the call on what

is and is not ready to ship

Responsibilities:

• Own the chip-level verification strategy, plan and signoff for a power-management controller program, from product requirements through tapeout, and present closure evidence and residual risk to engineering and program leadership.
• Architect the next-generation UVM verification environment for the controller family: the analog interface and real-number modeling strategy, register model integration with firmware-driven and non-volatile configuration, protocol agents for the power-management buses, reuse across derivatives, and a migration path that keeps the existing regression suite running throughout.
• Define and enforce verification methodology across the team: verification plan structure, coverage model and closure criteria, assertion and checker standards, coding guidelines and review practice.
• Lead technical reviews of verification plans, testbench architecture, checkers and coverage models written by other engineers, and mentor senior and junior engineers toward full ownership of their blocks.
• Decide where formal verification, gate-level simulation, FPGA or emulation add value beyond simulation, and drive their adoption.
• Own the verification infrastructure roadmap: regression dispatch on a compute grid, coverage merge and analytics, failure triage automation, and register and configuration generators, in Python, Perl and Tcl.
• Lead debug of the most difficult failures across RTL, testbench, firmware, analog models and specification, and turn root causes into methodology and checker improvements.
• Support silicon bring-up and validation, drive pre-silicon to silicon correlation, and run escape analysis that feeds back into the verification plan and methodology.
• Evaluate tools, verification IP and methodologies, and make build-versus-buy recommendations with cost and schedule justification.
• Estimate verification effort and staffing for new programs, and communicate status, risk and signoff evidence clearly to design, firmware, analog, validation, systems and program management.

Function: Manufacturing
Experience Level: Mid-Senior Level