Staff Verification Engineer
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Job Description
• This is a full-time, on-site role for a Senior Hardware Verification Engineer using UVM, located in Israel Raanana
• The role involves developing and maintaining UVM-based verification environments, writing testbenches, test cases, and coverage models for complex IP and SoC designs.
• The engineer will analyze specifications, define verification plans, create and execute verification scenarios, and debug RTL issues in close collaboration with design, architecture, and firmware teams.
• Daily tasks include running regressions, monitoring coverage metrics, performing root-cause analysis of failures, and contributing to continuous improvement of verification methodologies and automation.
• The role may also include mentoring junior engineers, participating in design and verification reviews, and aligning verification activities with project schedules and quality standards.
Requirements
Function: Manufacturing
Experience Level: Mid-Senior Level