Memory Layout Technical Lead
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Job Description
• Technical Domain
Layout design for non-volatile memory (NVM) IP, including Flash, MRAM, and ReRAM
• Target Products
MCUs for automotive, industrial, and IoT applications
• Project Overview
Layout design for NVM IP based on memory cells developed by in-house fabs and foundry partners
Contribute to PPA (Performance, Power, and Area) optimization of MCU products
Collaborate with global NVM development teams in Japan and overseas
• Responsibilities
Serve as the technical lead for the memory layout design team
Develop layout strategies based on IP requirements and circuit specifications
Lead hands-on layout design and verification activities
Renesas is expanding its investment in next-generation embedded NVM technologies and IP development to further strengthen the competitiveness of its MCUs for automotive, industrial, and IoT applications. As embedded NVM IP—including Flash and emerging memory technologies such as MRAM and ReRAM—is a key differentiator for MCUs, demand continues to grow for higher performance, greater capacity, and enhanced reliability.
This position is responsible for the layout design of embedded NVM IP for future MCUs. You will have the opportunity to develop a core technology that supports a world-leading MCU business shipping tens to hundreds of millions of units, enabling you to make a significant business impact. Renesas’ embedded NVM IP development organization also actively and continuously submits and presents papers at premier international semiconductor conferences, including ISSCC, the Symposium on VLSI Circuits, and IEDM. Working alongside highly skilled development engineers, you will be able to further deepen your expertise while gaining experience and broader skills across memory technologies.
Requirements
Function: Engineering
Experience Level: Mid-Senior Level