Staff Digital Mixed-Signal System Engineer

Renesas is seeking an experienced Staff Digital Mixed-Signal Systems Engineer to develop, model, and verify digitally implemented mixed-signal data paths for next-generation digital power management products used in AI, datacenter, and high-performance computing applications. 

This role focuses on the digital processing that connects real-world analog measurements to control-loop decisions. Areas of responsibility include ADC interfaces and controllers, front-end filtering, digital signal processing, telemetry paths, emulation models, timing behavior, fixed-point implementation, and hardware and firmware interfaces. 

The successful candidate will work closely with systems, digital design, firmware, verification, validation, applications, and analog design teams to translate product and feature requirements into executable models, detailed engineering specifications, RTL implementation requirements, and verification evidence. 

This is a digital systems engineering role for mixed-signal power products. It does not involve transistor-level analog circuit design, but it requires a solid understanding of analog behavior and its interaction with digital control and signal-processing functions. 

WHY THIS ROLE MATTERS 

• Develop the digital processing paths that connect sensed power-rail behavior to control-loop, telemetry, protection, and diagnostic functions. 

• Improve the modeling, observability, and verification of mixed-signal behavior in advanced digital power products. 

• Help engineering teams identify and resolve differences among system requirements, models, digital implementation, and measured behavior. 

• Create reusable models, test methods, and specifications that improve engineering execution across product development. 

KEY RESPONSIBILITIES 

• Develop digital mixed-signal data paths for digital multiphase power controllers and related power management products. 

• Design and evaluate front-end digital signal-processing functions that filter, condition, scale, decimate, observe, and route sensed voltage and current information. 

• Develop requirements for ADC interfaces and controllers, including sampling relationships, data-valid timing, channel sequencing, calibration support, latency, saturation, quantization, and error handling. 

• Create executable behavioral models and emulation-oriented representations that allow system and feature behavior to be evaluated before RTL and silicon are complete. 

• Translate system and control-loop requirements into detailed RTL requirements, fixed-point formats, datapath behavior, register definitions, firmware interfaces, and verification criteria. 

• Analyze fixed-point implementation tradeoffs involving numeric range, precision, quantization, rounding, saturation, latency, area, and implementation complexity. 

• Collaborate with analog design engineers to understand ADC, sensing, reference, timing, noise, and accuracy assumptions that affect digital implementation. 

• Work with firmware engineers to develop configuration, observability, debug, telemetry, and bring-up capabilities needed for characterization and customer support. 

• Work with design verification and validation engineers to develop reference scenarios, measurable pass/fail criteria, correlation methods, and test coverage for assigned features. 

• Analyze results from behavioral models, RTL simulations, emulation, bench testing, and silicon measurements to identify differences and support issue resolution. 

• Contribute to technical tradeoff decisions involving loop performance, latency, noise sensitivity, resolution, dynamic range, power, area, configurability, and customer-visible behavior. 

• Document data-path behavior, interfaces, assumptions, models, limits, corner cases, and verification expectations for cross-functional engineering teams. 

• Participate in technical reviews and communicate analysis, results, implementation risks, and recommended solutions. 

e contracts, model behavior, limits, corner cases, and validation expectations.

Function: Engineering
Experience Level: Mid-Senior Level