Staff Design Verification Engineer

We are seeking a highly skilled and motivated Staff Design Verification Engineer to join our hardware development team. In this role, you will be responsible for ensuring the functional correctness and robustness of complex digital and mixed-signal ASIC designs through advanced verification methodologies. You will work closely with architects, designers, and other verification engineers to deliver high-quality silicon solutions.

Responsibilities

• Develop and execute comprehensive verification plans for complex mixed-signal ASIC designs.
• Create and maintain testbenches using SystemVerilog/UVM.
• Write and debug test cases to verify functionality, performance, and corner cases.
• Perform block-level and full-chip verification, including simulation, coverage analysis, and regression run/debug.
• Collaborate with design engineers to understand specifications and identify verification requirements.
• Analyze and resolve issues found during verification and post-silicon validation.
• Mentor junior engineers and contribute to improving verification processes and infrastructure.
• Participate in code reviews and contribute to continuous improvement of design and verification practices.
• Manage and debug gate-level simulation (pre- and post- layout, with and without SDF timing annotation).

Function: Engineering
Experience Level: Mid-Senior Level